The present invention relates generally to a cache for a computer processor, and more specifically, to a cache including a non-data inclusive coherent (NIC) directory.
A symmetric multiprocessor (SMP) is a computer system that includes a plurality of processor nodes that are linked by one or more SMP buses. A computer system, such as an enterprise server computer system, may include multiple processor sockets that are interconnected in a SMP bus topology so as to achieve a relatively large overall processor capacity. Each processor node in a SMP includes a cache subsystem; a robust cache subsystem may be critical to good performance of a SMP. A relatively large SMP may have high traffic on the SMP bus, including snoops, which is a request for data by a processor node that is sent to the other processor nodes in the SMP, and cache-to-cache interventions, in which data migrates from one processor node to another. A snoop may require that a processor node interrogate a lower-level cache in the processor node to determine if the data requested by the snoop exists in the processor node. Such lower-level cache interrogations may interfere with core performance in the processor node.
An inclusive cache policy may be used in a multi-level cache hierarchy, allowing the highest-level cache to filter out snoops from the SMP bus when the requested data does not reside in the lower-level caches in the processor node. However, an inclusive cache policy may be relatively inefficient in use of available cache bits in the highest-level cache, as, in an inclusive cache, the highest-level cache holds the same data, or older versions of the data, that resides in the lower level caches. A victim highest-level cache that includes copies of the lower-level cache directories may also be used. However, such a caching structure requires a relatively large amount of space for the copied directories, and may also have relatively long shared intervention latency with owned data that is returned from a lower-level cache.